Vážení zákazníci, v letošním roce budeme expedovat poslední objednávky ve středu 18. 12. 2024.

Těšíme se s vámi na shledanou od pondělí 06. 01. 2025.

 

Cena s DPH / bez DPH
Hlavní stránka>BS IEC 62047-31:2019 Semiconductor devices. Micro-electromechanical devices Four-point bending test method for interfacial adhesion energy of layered MEMS materials
Sponsored link
sklademVydáno: 2019-04-17
BS IEC 62047-31:2019 Semiconductor devices. Micro-electromechanical devices Four-point bending test method for interfacial adhesion energy of layered MEMS materials

BS IEC 62047-31:2019

Semiconductor devices. Micro-electromechanical devices Four-point bending test method for interfacial adhesion energy of layered MEMS materials

Formát
Dostupnost
Cena a měna
Anglicky Zabezpečené PDF
K okamžitému stažení
4898 Kč
Čtěte normu po dobu 1 hodiny. Více informací v kategorii E-READING
Čtení normy
na 1 hodinu
489.80 Kč
Čtěte normu po dobu 24 hodin. Více informací v kategorii E-READING
Čtení normy
na 24 hodin
1469.40 Kč
Anglicky Tisk
Skladem
4898 Kč
Označení normy:BS IEC 62047-31:2019
Počet stran:16
Vydáno:2019-04-17
ISBN:978 0 580 96660 6
Status:Standard
Popis

BS IEC 62047-31:2019


This standard BS IEC 62047-31:2019 Semiconductor devices. Micro-electromechanical devices is classified in these ICS categories:
  • 31.080.99 Other semiconductor devices
IEC 62047-31:2019 (E) specifies a four-point bending test method for measuring interfacial adhesion energy of the weakest interface in the layered micro-electromechanical systems (MEMS) based on the concept of fracture mechanics. In a variety of MEMS devices, there are many layered material interfaces, and their adhesion energies are critical to the reliability of the MEMS devices. The four-point bending test utilizes a pure bending moment applied to a test piece of layered MEMS device, and the interfacial adhesion energy is measured from the critical bending moment for the steady state cracking in the weakest interface. This test method applies to MEMS devices with thin film layers deposited on semiconductor substrates. The total thickness of the thin film layers should be 100 times less than the thickness of a supporting substrate (typically a silicon wafer piece).