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sklademVydáno: 2021-08-19
BS IEC 62530:2021
SystemVerilog. Unified Hardware Design, Specification, and Verification Language
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| Označení normy: | BS IEC 62530:2021 |
| Počet stran: | 1320 |
| Vydáno: | 2021-08-19 |
| ISBN: | 978 0 539 17341 3 |
| Status: | Standard |
DESCRIPTION
BS IEC 62530:2021
This standard BS IEC 62530:2021 SystemVerilog. Unified Hardware Design, Specification, and Verification Language is classified in these ICS categories:
- 25.040.01 Industrial automation systems in general
- 35.060 Languages used in information technology
This standard provides the definition of the language syntax and semantics for the IEEE 1800™ SystemVerilog language, which is a unified hardware design, specification, and verification language. The standard includes support for behavioral, register transfer level (RTL), and gate-level hardware descriptions; testbench, coverage, assertion, object-oriented, and constrained random constructs; and also provides application programming interfaces (APIs) to foreign programming languages.