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Homepage>IEC 63011-1:2018 - Integrated circuits - Three dimensional integrated circuits - Part 1: Terminology
sklademVydáno: 2018-11-28
IEC 63011-1:2018 - Integrated circuits - Three dimensional integrated circuits - Part 1: Terminology

IEC 63011-1:2018

Integrated circuits - Three dimensional integrated circuits - Part 1: Terminology

Circuits intégrés - Circuits intégrés tridimensionnels - Partie 1 : Terminologie

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Označení normy:IEC 63011-1:2018
Vydáno:2018-11-28
Jazyk:Anglicky/Francouzsky
DESCRIPTION

IEC 63011-1:2018

IEC 63011-1:2018 provides definitions pertaining to multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. Terms and definitions related to the fabrication and test of the multichip integrated circuits are also provided.

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